A silicon single crystal is produced by pulling up and growing using the CZ (Czochralski) method. An ingot of the pulled-up and grown silicon single crystal is sliced into silicon wafers. A semiconductor device is fabricated through a device process in which a device layer is formed on the surface of a silicon wafer.
However, a crystal defect referred to as the “grown-in defect” (defect incurred during the crystal growth) occurs in the course of the growth of a silicon single crystal.
Recently, as the semiconductor circuit becomes more dense and fine, the presence of such grow-in defects has become intolerable in the vicinity of a surface layer of a silicon wafer where a device is fabricated. Thus, studies are being conducted on the possibility of producing a defect-free crystal.
In general, there are the following three types of crystal defects which may be included in a silicon single crystal and deteriorate device characteristics.
i) Void defect generated by aggregation of vacancies and referred to as COP (Crystal Originated Particles) or the like
ii) OSF (Oxidation Induced Stacking Fault)
iii) Dislocation loop clusters generated by aggregation of interstitial silicon (also known as interstitial silicon dislocation defects, or I-defects)
A defect-free silicon single crystal is recognized or defined as a crystal not including or substantially not including any of the three types of defects.
It is known that the generation behaviors of the above-mentioned three types of defects vary as described below depending on growth conditions. Description will be made with reference to FIG. 1. In FIG. 1, the horizontal axis represents the growth condition V/G (V denotes a growth rate, and G denotes temperature gradient in the axial direction in the vicinity of the melting point of a silicon single crystal). Assuming that G is fixed, G can be considered as a function of the growth rate V. The vertical axis in FIG. 1 represents the point defect concentration.
i) When the growth rate V is high, the silicon single crystal will have an excess of vacancy point defects, and only void defects will occur.
ii) When the growth rate V is decreased, ring-shaped OSFs (R-OSFs) occur near the outer periphery of the silicon single crystal 10, resulting in a structure in which void defects are present in the inside of the R-OSF portion.
iii) When the growth rate V is decreased further, the radius of the ring-shaped OSFs (R-OSFs) will decrease, resulting in a structure in which a region that does no contain the defects is formed in the outside of the ring-shaped OSFs, and void defects are present in the inside of the R-OSF portion.
iv) When the growth rate V is decreased even further, the resulting structure is such that dislocation loop clusters are present in the entire silicon single crystal.
The reason why the above-mentioned phenomena occur is believed to be that as the growth rate V decreases, the silicon single crystal changes from a state of excess of vacancy point defects to a state of excess of interstitial silicon point defects, and this change is understood to start from the outer periphery of the silicon single crystal.
In FIG. 1, the regions where the void defects are present at high density are referred to as the “V-rich region” (vacancy point defect rich region) and the “I-rich region” (interstitial point defect rich region).
Of the above three types of defect, the void defects in particular constitute a cause of device isolation failure in very small devices, so there is a particular need to reduce such defects.
The void defects are produced when atomic vacancies (point defects) incorporated from a silicon melt during crystal growth agglomerate as a result of reaching a critical supersaturation during crystal cooling, and are called LPD (laser particle defect), COP (crystal oriented particle), FPD (flow pattern defect), LSTD (laser scattering tomography defect), and so forth depending on methods for detecting such defects.
A defect-free silicon single crystal is recognized or defined as a crystal not including, or substantially not including any of the above three types of defects.
There have been proposed methods as follows to obtain a silicon wafer including no grow-in defect near the surface layer where a device circuit is to be fabricated.
i) To manufacture a defect-free single crystal ingot by controlling crystal growth conditions
ii) To vanish void defects near the wafer surface layer by high-temperature annealing
iii) To form a defect-free layer on the wafer surface by epitaxial growth
Among these methods, the method to vanish void defects near the wafer surface layer by high-temperature annealing is already a well known technique. Specifically, according to this method, a silicon wafer is obtained from a silicon single crystal grown under ordinary growth conditions and including void defects, and the obtained wafer is subjected to a thermal treatment at a high temperature for long period of time to thereby vanish void defect near the surface layer (hereinafter, the wafer shall be referred to as the “annealed wafer”).
Additionally, an oxygen deposit referred to as BMD (bulk micro defect) is generated during a thermal treatment in device manufacturing processes. Control of the BMD generation constitutes an important problem in the manufacture of a silicon wafer. Specifically, any BMDs formed near the surface layer where a device circuit is to be fabricated will impair the functions of the device.
On the other hand, the presence of any heavy metal impurity such as Fe or Cu in a surface layer portion of a silicon wafer will deteriorate device characteristics when the device is fabricated. This makes it necessary to form a gettering site for capturing the heavy metal within the bulk of the silicon wafer. The BMD generated within the bulk of the silicon wafer will effectively act as the gettering (intrinsic gettering) source for capturing the heavy metal.
FIG. 2 schematically shows a cross-sectional structure of an annealed wafer.
As seen from the description above, it is necessary for the manufacture of an annealed wafer 100 as shown in FIG. 2 to form, within the wafer 100, an intrinsic gettering site having BMDs at a high density of approximately 108 unit/cm3 or more, while forming a defect-free layer including no BMDs nor grow-in defects such as COP as described above, namely a DZ layer, in the surface layer where a device is to be fabricated (with a depth of 10 μm or more). Thus, there is a strong demand for achieving easy commercial manufacture of such annealed wafers.
The COP or BMD density is affected by an oxygen concentration within a silicon single crystal. Therefore, the oxygen concentration within a silicon single crystal constitutes an important factor in manufacturing an ideal annealed wafer.
In order to facilitate the elimination of COPs generated by the annealing treatment, a method is taken of doping the silicon single crystal with nitrogen to reduce the initial size of the COPs. This is described in Patent Document 2. The nitrogen doping also makes it possible to produce an increased quantity of BMDs.
In this manner, the size of the COPs and the quantity of the BMDs are affected by a nitrogen concentration.
In order to manufacture an ideal annealed wafer as described above, the control of the oxygen concentration and the nitrogen concentration within the silicon single crystal forming a substrate thereof constitutes an important factor.
A method is also known of reducing the amount of vacancies incorporated in the silicon single crystal and reducing the COP size by decreasing the pulling growth rate, or reducing the ratio V/G between the pulling rate V and the temperature gradient G in the vicinity of the melting point, in the course of growth of the crystal.
When a silicon wafer with a diameter of 200 mm is manufactured, the crystal can be pulled at a very high rate. As the pulling rate is increased, the cooling rate of the silicon single crystal is also increased, and the residence time in a temperature range in which COPs are formed is shortened, resulting in reduction of the COP size.
However, when a silicon wafer with a diameter of 300 mm is manufactured, the heat capacity of a silicon ingot is increased, and hence the cooling rate of the silicon single crystal cannot be increased enough to reduce the COP size.
Therefore, when manufacturing a silicon wafer with a diameter of 300 mm, a method is taken of conversely reducing the pulling rate, setting various conditions and then reducing the COP size.
More specifically, referring to FIG. 1, a silicon single crystal with a diameter of 300 mm is often pulled under crystal growth conditions corresponding to a V/G region overlapping with an R-OSF region. In this low V/G region, the quantity of vacancies incorporated in the silicon single crystal is reduced, and hence the size and density of the COPs can be reduced. This makes it easy to eliminate the COPs generated by annealing. However, the silicon single crystal thus obtained is a slow cooling type crystal that is to be cooled slowly.
It has conventionally been believed that an ideal annealed wafer 100 as shown in FIG. 2 can be easily manufactured commercially by taking the methods as described above.
Recently, however, a defect called DNN defect having a different origin from the void defect (COP) has been found in the surface layer of an annealed wafer.
The DNN defect means a wafer surface defect that is detected by measurement in the DNN (dark-field normal narrow) mode using a commercially available Particle Counter SP1 (instrument made by KLA-Tencor). The DNN mode is a mode in which laser light is applied vertically to the wafer and then collected in a portion close to regular reflection to observe the diffuse reflection due to defects. The DNN mode is particularly effective to detect foreign particles and pits (depressions) on the wafer surface.
Patent Document 1, which is described later, discloses an invention according to which DNN defects are reduced by performing hydrofluoric acid cleaning prior to annealing in order to dissolve oxygen deposits which serve as cores of DNN defects and is generated after annealing.
Patent Document 1 also describes the following findings about relationship among DNN defects, oxygen concentration, nitrogen concentration, and crystal growth conditions.
1) There is described a finding that the quantity of DNN defects is increased as the oxygen concentration in a silicon single crystal is increased (Patent Document 1, paragraph (0023)).
2) There is described a finding that a greater quantity of DNN defects are generated in an annealed wafer containing nitrogen than in an annealed wafer containing no nitrogen (Patent Document 1, paragraph (0020)).
3) There is described a finding that many DNN defects are generated when a silicon single crystal is pulled and grown under crystal growth conditions corresponding to a region where OSFs tend to occur, and therefore the generation of DNN defects can be reduced by pulling and growing the silicon single crystal under crystal growth conditions corresponding to a region where less OSFs occur, while avoiding the region where OSFs tend to occur (Patent Document 1, paragraph (0057)).
Patent Document 1: Japanese Patent application Laid-Open No. 2004-119446
Patent Document 2: Japanese Patent No. 3479001